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Integrated Circuit Systems, Inc.
ICSSSTUA32S865A
28-Bit Registered Buffer for DDR2
Recommended Application: * DDR2 Memory Modules * Provides complete DDR DIMM solution with ICS97U877 * Ideal for DDR2 400, 533 and 667 Product Features: * 28-bit 1:2 registered buffer with parity check functionality * Supports SSTL_18 JEDEC specification on data inputs and outputs * Supports LVCMOS switching levels on CSR# and RESET# inputs * Low voltage operation VDD = 1.7V to 1.9V * Available in 160 BGA package * Green packages available
Pin Configuration
1 A B C D E F G H J K L M N P R T U V 2 3 4 5 6 7 8 9 10 11 12
+++ + + + + + + + + + + + + +++
+++++ + + ++ + ++ + ++ + ++ + ++ + ++ + ++ + ++ + + + +++++
Functionality Truth Table
In puts RESET# H H H H H H H H H H H H H H H L DCS0# L L L L L L H H H H H H H H H X or floating DCS1# L L L H H H L L L H H H H H H X or floating CSGate Enable X X X X X X X X X L L L H H H X or floating CK L or H L or H L or H L or H L or H X or floating CK# L or H L or H L or H L or H L or H X or floating Dn, DODTn, DCK En L H X L H X L H X L H X L H X X or floating Qn L H Q0 L H Q0 L H Q0 L H Q0 Q0 Q0 Q0 L Outputs QCS# L L Q0 L L Q0 H H Q0 H H Q0 H H Q0 L QODT, QCKE L H Q0 L H Q0 L H Q0 L H Q0 L H Q0 L
160 Ball BGA (Top View)
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ICSSSTUA32S865A
Ball Assignments
1 A B C D E F G H J K L M N P R T U V
VREF D1 D3 D6 D7 D11 D18 NC D2 D4 D5 D8 D9 D12 VDDL VDDL VDDL VDDL VDDL GND VDDL GND GND VDDL GND GND GND GND GND GND GND GND VDDL GND GND VDDL VDDL VDDL VDDL VDDL VDDR GND NC VDDL NC VDDR GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR VDDR GND GND GND VDDR VDDR GND VDDR GND VDDR GND VDDR GND GND
2
NC
3
PARIN NC NC
4
NC NC
5
6
QCKE1A QCKE1B
7
QCKE0A QCKE0B
8
Q21A Q21B
9
Q19A Q19B
10
Q18A Q18B
11
Q17B
QODT0B QODT1B
12
Q17A
QODT0A QODT1A
Q20B Q16B Q1B Q2B Q5B
Q20A Q16A Q1A Q2A Q5A
CSGate D15 EN CK CK# DCS0# DCS1#
QCS0B# QCS0A# QCS1B# QCS1A# Q6B Q10B Q9B Q11B Q15B Q14B Q6A Q10A Q9A Q11A Q15A Q14B Q8B Q8A
RESET# D14 D0 D17 D19 D13 DODT1 DCKE0 VREF D10 D16 D21 D20 DODT0 DCKE1 MCL MCL MCL
PTYERR# MCH
Q3B Q3A
Q12B Q12A
Q7B Q7A
Q4B Q4A
Q13B Q13A
Q0B Q0A
NC
MCH
Note: An empty cell indicates no ball is populated at that gridpoint. NC denotes a no-connect (ball present but not connected to the die). MCL denotes a pin that Must be Connected LOW. MCH denotes a pin that Must be Connected HIGH.
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ICSSSTUA32S865A
General Description
This 28-bit 1:2 registered buffer with parity is designed for 1.7V to 1.9V VDD operation. All clock and data inputs are compatible with the JEDEC standard for SSTL_18. The control inputs are LVCMOS. All outputs are 1.8 V CMOS drivers that have been optimized to drive the DDR2 DIMM load. The ICSSSTUA32S865A operates from a differential clock (CK and CK#). Data are registered at the crossing of CK going high, and CK# going low. The device supports low-power standby operation. When the reset input (RESET#) is low, the differential input receivers are disabled, and undriven (floating) data, clock and reference voltage (VREF) inputs are allowed. In addition, when RESET# is low all registers are reset, and all outputs except PTYERR# are forced low. The LVCMOS RESET# input must always be held at a valid logic high or low level. To ensure defined outputs from the register before a stable clock has been supplied, RESET# must be held in the low state during power up. In the DDR2 RDIMM application, RESET# is specified to be completely asynchronous with respect to CK and CK#. Therefore, no timing relationship can be guaranteed between the two. When entering reset, the register will be cleared and the outputs will be driven low quickly, relative to the time to disable the differential input receivers. However, when coming out of reset, the register will become active quickly, relative to the time to enable the differential input receivers. As long as the data inputs are low, and the clock is stable during the time from the low-to-high transition of RESET# until the input receivers are fully enabled, the design of the ICSSSTUA32S865A must ensure that the outputs will remain low, thus ensuring no glitches on the output. The device monitors both DCS0# and DCS1# inputs and will gate the Qn outputs from changing states when both DCS0# and DCS1# are high. If either DCS0# or DCS1# input is low, the Qn outputs will function normally. The RESET# input has priority over the DCS0# and DCS1# control and will force the Qn outputs low and the PTYERR# output high. If the DCS-control functionality is not desired, then the CSGateEnable input can be hardwired to ground, in which case, the setup-time requirement for DCS would be the same as for the other D data inputs. The ICSSSTUA32S865A includes a parity checking function. The ICSSSTUA32S865A accepts a parity bit from the memory controller at its input pin PARIN, compares it with the data received on the D-inputs and indicates whether a parity error has occurred on its open-drain PTYERR# pin (active LOW). Package options include 160-ball Thin Profile Fine Pitch BGA (TFBGA) (12 X 18 array, 9.0 X 13.0 mm body size, 0.65 mm pitch, MO-246, Issue A).
Inputs RESET# H H H H H H H H H H L DCS0# L L L L H H H H H X X or floating DCS1# H H H H L L L L H X X or floating CK L or H X or floating CK# L or H X or floating of inputs = H (D0-D21) Even Odd Even Odd Even Odd Even Odd X X X or floating PARIN* L L H H L L H H X X X or floating
Output PTYERR#** H L L H H L L H
PTYERR# 0 PTYERR# 0
H
*
PARIN arrives one clock cycle after the data to which it applies.
** This transition assumes PTYERR# is high at the crossing of CK going high and CK# going low. If PTYERR# is low, it stays latched low for two clock cycles or until RESET# is driven low.
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ICSSSTUA32S865A
Ball Assignment
Signal Group Signal Name Type Description DRAM function pins not associated with Chip Select. DRAM inputs, re-driven only when Chip Select is LOW. DRAM Chip Select signals. These pins initiate DRAM address/command decodes, and as such at least one will be low when a valid address/command is present. The register can be programmed to re-drive all D-inputs only (CSGateEN high) when at least one Chip Select input is LOW. Outputs of the register, valid after the specified clock count and immediately following a rising edge of the clock.
Ungated inputs DCKE0, DCKE1, SSTL_18 DODT0, DODT1 Chip Select gated inputs Chip Select inputs D0 ... D21 DCS0# , DCS1# SSTL_18 SSTL_18
Re-driven outputs
Q0A...Q21A, Q0B ... Q21B, QCS#0-1A,B, QCKE0-1A,B, QODT0-1A,B PARIN
SSTL_18
Parity input
SSTL_18
Input parity is received on pin PARIN and should maintain odd parity across the D0...D21 inputs, at the rising edge of the clock. When LOW, this output indicates that a parity error was identified associated with the address and/or command inputs. PTYERR# will be active for two clock cycles, and delayed by an additional clock cycle for compatibility with final parity out timing on the industry-standard DDR-II register with parity (in JEDEC definition). Chip Select Gate Enable. When HIGH, the D0..D21 inputs will be latched only when at least one Chip Select input is LOW during the rising edge of the clock. When LOW, the D0...D21 inputs will be latched and redriven on every rising edge of the clock. Differential master clock input pair to the register. The register operation is triggered by a rising edge on the positive clock input (CK). Must be connectedd to a logic LOW or HIGH.
Parity error output
PTYERR#
Open drain
Program inputs CSGateEN
1.8 V LVCMOS
Clock inputs
CK, CK#
SSTL_18
Miscellaneous inputs
MCL, MCH RESET# 1.8 V LVCMOS
Asynchronous reset input. When LOW, it causes a reset of the internal latches, thereby forcing the outputs LOW. RESET# also resets the PTYERR# signal.
VREF
0.9 V nominal Input reference voltage for the SSTL_18 inputs. Two pins (internally tied together) are used for increased reliability.
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ICSSSTUA32S865A
Block Diagram
(CS ACTIVE) VREF PARITY GENERATOR AND CHECKER
PARIN
D R
Q 22
PTYERR#
Q0A D0 D R Q21A D21 D R QCS0A# D R CSGateEN
DCS1#
Q Q0B
Q Q21B
DCS0#
Q QCS0B#
QCS1A# D R QCKE0A, QCKE1A QCKE0B, QCKE1B QODT0A, QODT1A QODT0B, QODT1B Q QCS1B#
DCKE0, DCKE1
2 D R Q
2
DODT0, DODT1
2 D R Q
2
RESET# CK CK#
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ICSSSTUA32S865A
Parity Functionality Block Diagram
22 Dn DQ 22
QnA
QnB
D
D
LATCHING AND RESET FUNCTION see Note (1)
PTYERR#
PARIN
D
(1) This function holds the error for two cycles. See functional description and timing diagram.
CLOCK
002aaa417
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ICSSSTUA32S865A
Register Timing
RESET#
DCSn#
n CK
n+1
n+2
n+3
n+4
CK#
tACT
tsu
th
Dn (1) tPDM, tPDMSS CK to Q Qn
tsu
th
PARIN tPHL CK to PTYERR# PTYERR# tPHL, tPLH CK to PTYERR#
H, L, or X
H or L
002aaa983
Figure 4 -- RESET# switches fr om L to H
(1) After RESET# is switched from LOW to HIGH, all data and PARIN input signals must be set and held LO W for minimum time of tACT (max.) to avoid false error.
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ICSSSTUA32S865A
Register Timing
RESET#
DCSn#
n CK
n+1
n+2
n+3
n+4
CK# tsu th
Dn (1) tPDM, tPDMSS CK to Q Qn tsu
th
PARIN tPHL, tPLH CK to PTYERR# PTYERR#
002aaa984
Unknown input e vent
Output signal is dependent on the pr unkno event ior wn
H or L
Figure 5 -- RESET# being held HIGH
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ICSSSTUA32S865A
Register Timing
RESET#
tINACT
DCSn#
CK (1)
CK# (1)
Dn (1) tRPHL RESET# to Q
Qn
PARIN (1) tRPLH RESET# to PTYERR# PTYERR#
002aaa985
H, L, or X
H or L
Figure 6 -- RESET# switches fr om H to L
(1) After RESET# is switched from HIGH to LOW , all data and cloc input signal must be set and held at valid logic levels (not floating) for a minimum tim of tINACT (max.).
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ICSSSTUA32S865A
Absolute Maximum Ratings
Storage Temperature . . . . . . . . . . . . . . . . . . . . Supply Voltage . . . . . . . . . . . . . . . . . . . . . . . . . Input Voltage1 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Output Voltage1,2 . . . . . . . . . . . . . . . . . . . . . . . . . . . . . Input Clamp Current . . . . . . . . . . . . . . . . . . . . Output Clamp Current . . . . . . . . . . . . . . . . . . . Continuous Output Current . . . . . . . . . . . . . . . VDDQ or GND Current/Pin . . . . . . . . . . . . . . . Package Thermal Impedance3
...............
-65C to +150C -0.5 to 2.5V -0.5 to VDD + 2.5V -0.5 to VDDQ + 0.5 50 mA 50mA 50mA 100mA 36C
Notes: 1. The input and output negative voltage ratings may be excluded if the input and output clamp ratings are observed. 2. This current will flow only when the output is in the high state level V0 >VDDQ. 3. The package thermal impedance is calculated in accordance with JESD 51.
Stresses above those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only and functional operation of the device at these or any other conditions above those listed in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect product reliability.
Recommended Operating Conditions
PARAMETER VDD VREF VTT VI V IH (DC) V IH (AC) V IL (DC) V IL (DC) VIH VIL VICR VID IOH IOL TA
1
DESCRIPTION I/O Supply Voltage Reference Voltage Termination Voltage Input Voltage DC Input High Voltage AC Input High Voltage Data Inputs DC Input Low Voltage AC Input Low Voltage RESET#, Input High Voltage Level C0, C1 Input Low Voltage Level Common mode Input Range CLK, CLK# Differential Input Voltage High-Level Output Current Low-Level Output Current Operating Free-Air Temperature
MIN TYP 1.7 1.8 0.49 x VDD 0.5 x V DD VREF - 0.04 V REF 0 V REF + 0.125 V REF + 0.250
MAX 1.9 0.51 x V DD VREF + 0.04 V DDQ
UNITS
VREF - 0.125 VREF - 0.250 0.65 x V DDQ 0.675 0.600 0.35 x V DDQ 1.125 -8 8 70
V
mA C
0
Guaranteed by design, not 100% tested in production. Note: Reset# and Cn inputs must be helf at valid logic levels (not floating) to ensure proper device operation. The differential inputs must not be floating unless Reset# is low.
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ICSSSTUA32S865A
Electrical Characteristics - DC
TA = 0 - 70C; V DD = 2.5 +/-0.2V, V DDQ=2.5 +/-0.2V; (unless otherwise stated) SYMBOL PARAMETERS V OH V OL All Inputs II Standby (Static) I DD Operating (Static) CONDITIONS I OH = -6mA I OL = 6mA V I = V DD or GND RESET# = GND V I = V IH(AC) or V IL(AC), RESET# = VDD RESET# = VDD, Dynamic operating V I = V IH(AC) or V IL(AC), (clock only) CLK and CLK# switching 50% duty cycle. IO = 0 RESET# = VDD, V I = V IH(AC) or V IL (AC), Dynamic Operating CLK and CLK# switching (per each data input) 50% duty cycle. One data input switching at half clock frequency, 50% duty cycle V I = V REF 350mV Data Inputs V ICR = 1.25V, V I(PP) = 360mV CLK and CLK# V I = V DDQ or GND RESET# V DDQ 1.7V 1.7V 1.9V 1.9V 80 TBD MIN 1.2 TYP MAX 0.5 5 200 UNITS
A A mA
/clock MHz
I DDD
1.8V TBD A/ clock MHz/data
Ci
2.5 2 2.5
3.5 3
pF
Notes: 1 - Guaranteed by design, not 100% tested in production.
Output Buffer Characteristics
Output edge rates over recommended operating free-air temperature range (See figure 7) VDD = 1.8V 0.1V PARAMETER UNIT MIN MAX dV/dt_r 1 4 V/ns dV/dt_f 1 4 V/ns 1 dV/dt_ 1 V/ns 1. Difference between dV/dt_r (rising edge rate) and dV/dt_f (falling edge rate)
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ICSSSTUA32S865A
Timing Requirements
(over recommended operating free-air temperature range, unless otherwise noted) VDD = 1.8V 0.1V SYMBOL PARAMETERS MIN MAX f clock Clock frequency 410 Pulse duration 1 tW Differential inputs active time 10 tACT t INACT tS Setup time Hold time tH Hold time Notes: Differential inputs inactive time Data before CLK, CLK# DCS0, DSC1# before CK, CK#, CSR# high DCS#, DODT, DCKE and Q after CK, CK# PAR_IN after CK, CK# 0.5 0.7 0.50 0.50 ns ns ns 15 UNITS MHz ns ns ns
1 - Guaranteed by design, not 100% tested in production. 2 - For data signal input slew rate of 1V/ns. 3 - For data signal input slew rate of 0.5V/ns and < 1V/ns. 4 - CLK/CLK# signal input slew rate of 1V/ns.
Switching Characteristics
(over recommended operating free-air temperature range, unless otherwise noted) Measurement Symbol Parameter MIN MAX Conditions fmax tPDM Max input clock frequency 410 1.25 1.2 1 1.9 3 3 2 3 3 Units MHz ns ns ns ns ns ns
Propagation delay, single CK to CK# QN bit switching Low to High propagation CK to CK# to tLH delay PTYERR# High to low propagation CK to CK# to tHL delay PTYERR# Propagation delay tPDMSS CK to CK# QN simultaneous switching High to low propagation tPHL Reset# to QN delay Low to High propagation tPLH Reset# to PTYERR# delay 1. Guaranteed by design, not 100% tested in production.
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ICSSSTUA32S865A
VDD
DUT td = 350ps TL =50 CK Inputs Test Point RL = 100 Test Point VCMOS RST# Inp ut t in act IDD (see Note 2) LOAD CIRCUIT VDD VDD/2 VDD/2 0V t act 90% 10% VOLTAGE AND CURRENT WAVEFORMS INPUTS ACTIVE AND INACTIVE TIMES tw Inpu t VICR VICR LVCMOS RST# Input VIH VDD /2 t RPHL t su Inpu t VREF th VREF VIH VOH Output VTT VOL VIL V ID Output VTT V TT CK VICR CK t PLH t PHL VOH VOL VICR CK# CK TL=350ps, 50 Out CL = 30 pF (see Note 1) RL = 1000 Test Point RL = 1000
VID
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
VOLTAGE WAVEFORMS - PULSE DURATION VID CK VICR CK
VIL VOLTAGE WAVEFORMS - SETUP AND HOLD TIMES
VOLTAGE WAVEFORMS - PROPAGATION DELAY TIMES
Figure 6 -- Parameter M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL incluces probe and jig capacitance. 2. IDD tested with clock and data inputs held at VDD or GND, and Io = 0mA. 3. All input pulses are supplied by generators having the following chareacteristics: PRR 10 MHz, Zo=50, input slew rate = 1 V/ns 20% (unless otherwise specified). 4. The outputs are measured one at a time with one transition per measurement. 5. VREF = VDD/2 6. VIH = VREF + 250 mV (ac voltage levels) for differential inputs. VIH = VDD for LVCMOS input. 7. VIL = VREF - 250 mV (ac voltage levels) for differential inputs. VIL = GND for LVCMOS input. 8. VID = 600 mV 9. tPLH and tPHL are the same as tPDM.
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ICSSSTUA32S865A
VDD DUT RL = 50 Out C L = 10 pF (see Note 1) Test Point
LOAD CIRCUIT - HIGH-TO-LOW SLEW-RATE MEASUREMENT Output 80% 20% dv _f dt _f VOL VOH
VOLTAGE WAVEFORMS - HIGH-TO-LOW SLEW-RATE MEASUREMENT
DUT
Out CL = 10 pF (see Note 1)
Test Point RL = 50
LOAD CIRCUIT - LOW-TO-HIGH SLEW-RATE MEASUREMENT dv _r dt _r 80% 20% Output VOL VOLTAGE WAVEFORMS - LOW-TO-HIGH SLEW-RATE MEASUREMENT VOH
Figure 7 -- Output Slew-Rate M easurement I nfor mation (V DD = 1.8 V 0.1 V)
Notes: 1. CL includes probe and jig capacitance. 2. All input pulses are supplied by generators having the following characteristics: PRR 10MHz, ZO = 50, input slew rate = 1 V/ns 20% (unless otherwise specified).
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ICSSSTUA32S865A
Output slew rate measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified. 10 MHz;
VDD
DUT
RL = 50
OUT CL = 10 pF SEE NOTE (1)
TEST POINT
002aaa377
(1) CL includes probe and jig capacitance.
Figure 12 -- Load circuit, HIGH-to-LOW slew measurement
OUTPUT 80% dv_f 20% dt_f
VOH
VOL
002aaa378
Figure 13 -- Voltage waveforms, HIGH-to-LOW slew rate measurement
DUT
OUT CL = 10 pF SEE NOTE (1)
TEST POINT RL = 50
002aaa379
(1) CL includes probe and jig capacitance.
Figure 14 -- Load circuit, LOW-to-HIGH slew measurement
dt_r VOH 80% dv_r 20% OUTPUT VOL
002aaa380
Figure 15 -- Voltage waveforms, LOW-to-HIGH slew rate measurement
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ICSSSTUA32S865A
Error output load circuit and voltage measurement information (VDD = 1.8 V 0.1 V) All input pulses are supplied by generators having the following characteristics: PRR Zo = 50 ; input slew rate = 1 V/ns 20%, unless otherwise specified.
VDD DUT RL = 1 k OUT CL = 10 pF SEE NOTE (1)
002aaa500
10 MHz;
TEST POINT
(1) CL includes probe and jig capacitance.
Figure 16 -- Load circuit, error output measurements
LVCMOS RESET Input
VCC VCC/2 0V tPLH VOH
Output Waveform 2
0.15 V
002aaa501
0V
Figure 17 -- Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to RESET input
Timing Inputs
VICR
VICR
VI(PP)
tHL VCC Output Waveform 1 VCC/2 VOL
002aaa502
Figure 18 -- Voltage waveforms, open-drain output HIGH-to-LOW transition time with respect to clock inputs
Timing Inputs
VICR
VICR
VI(PP)
tLH VOH Output Waveform 2
0.15 V
002aaa503
0V
Figure 19 -- Voltage waveforms, open-drain output LOW-to-HIGH transition time with respect to clock inputs
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ICSSSTUA32S865A
A2
0.925 Ref b
ROW A, COLUMN 1
A3
12 11 10 9 8 7 6 5 4 3 2 1 A B C D E F G E1 H J K L M N P R T U V e/2 D1 C e TYP
E
e/2
TOP VIEW
A1 D A
0.975 Ref
Ball Grid Array (FBGA) 160 Balls, 9x13 mm, 12x18 Pattern
SYMBOL A A1 A2 A3 b D D1 E E1 e MIN. 0.90 0.25 0.20 0.45 0.35 MILLIMETER NOM. MAX. 1.05 1.20 0.30 0.35 0.25 0.30 0.50 0.55 0.40 0.45 9.00 BSC 7.15 BSC 13.00 BSC 11.05 BSC 0.65 BSC MIN. 0.035 0.010 0.009 0.018 0.014 INCH* NOM. 0.041 0.012 0.010 0.020 0.016 0.354 BSC 0.281 BSC 0.512 BSC 0.435 BSC 0.026 BSC MAX. 0.047 0.014 0.012 0.022 0.018
* For Reference Only. Controlling dimensions in mm.
Ordering Information
ICSSSTUA32S865AH(LF)-T
Example:
ICS XXXX y H (LF)- T
Designation for tape and reel packaging Annealed Lead Free (Optional) Package Type H = BGA Revision Designator (will not correlate with datasheet revision) Device Type Prefix ICS = Standard Device
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